As is well known, the fabrication of integrated electronic devices on semiconductor substrates often requires that the circuit patterns be checked for critical architectures which might impair a reliable operation of the formed components.
In particular, this test is necessary where a conductive layer is to be deposited onto a surface less than truly planar, having local discontinuities or depressions. In fact, the conductive layer of the latest deposition, due to low conformability of the deposited film, may have its cross-section reduced in size so that in some cases mechanical breaks occur producing loss of electrical continuity.
A typical instance is that of a plurality of active elements, whose gate regions extend across the substrate as discrete parallel lines, e.g. in the form of floating gate lines, which require reduction to a planar type architecture for receiving, as by deposition, an overlying conductive layer. On analyzing a vertical cross-section of the semiconductor substrate under an electronic microscope, a typical square-wave profile can be observed, as shown in FIG. 1. This profile is obviously unsuitable to receive a deposition of conductive material thereon. To effect a subsequent deposition of a conductive layer, the cross-section profile must be made less "discontinuous."
Merely as an example, consider an instance where a plurality of floating gates are to be intersected orthogonally by a plurality of strips of a conductive material to define a topography of the matrix type, that is a typical structure of semiconductor memory circuits such as those including EPROM or E.sup.2 PROM memory cells. The plurality of parallel lines including the floating gates will be referred to as the "bit lines", and the plurality of conductive strips referred to as the "word lines," hereinafter. FIG. 2 illustrates a plurality of EPROM memory cells under an electronic microscope having a matrix-like topography resulting from intersecting bit and word lines. It is a recognized fact, in this particular application, that conductive layers deposited over semiconductor substrates tend to distribute themselves unevenly across the substrate, thereby developing discontinuous profiles wherein areas of substantial thickness alternate with areas of diminishing thickness. The more pronounced this feature is, the more discontinuous the cross-sectional semiconductor profile will be.
Shown in FIGS. 3 and 4 is a perspective view of a semiconductor substrate having a plurality of bit lines 6 integrated thereon which are laid parallel to and at a spacing from one another. The bit lines 6 may include EEPROM and FLASH EPROM memory cells when orthogonally intersected at the top by a plurality of parallel spaced conductive strips 12 as shown in FIG. 4. This plurality of conductive strips 12 are customarily referred to as the word lines. Conductive strips 12 may include a first layer 10 and a second layer 11.
Each bit line 6 deposited over the semiconductor substrate 1, at predetermined areas thereof, comprises:
a first thin oxide layer 2 referred to as the tunnel or gate oxide;
a second layer 3 of polysilicon, also referred to as the polyl;
a third, insulating layer 4, typically of ONO (Oxide-Nitride-Oxide); and
a fourth layer 5 of polysilicon, also referred to as the poly cap.
Thus, a circuit architecture 9 is formed on substrate 1 which includes bit lines 6 and word lines 12 to provide, for example, EPROM or FLASH memory cells. Voids 7 are formed between bit lines 6.
The deposition areas of the conductive layer where thickness is the smallest are susceptible to mechanical breaks that destroy the electrical continuity of the layer. In addition, another drawback shows up when the plurality of regions or voids 7 in the semiconductor substrate 1, bounded by the bit lines 6, must be isolated electrically from the overlying conductive layer. In fact, if the substrate is isolated by silicon oxide, the oxide thermal growth may reveal diminishing thickness at the edges of the bit line 6 forming a topography which is difficult to cover in conformal way by the conductive layer.
As to the word lines 12, these are conventionally formed from the deposited conductive layer defined by photolithographic and either wet or dry etching operations.
FIG. 5 is an enlarged scale view obtained from a photograph taken by an electronic microscope showing a vertical cross-section through a semiconductor substrate integrating a plurality of bit lines which are isolated from one another by a deposition of dielectric oxide and are covered with a conductive layer. This figure highlights another drawback which is typically associated with the deposition of the conductive layer. This drawback is noticeable in the black area at the top of the picture. The black area actually shows narrower portions near a white area identifying the oxide layer which separates the bit line from the conductive layer. These narrower portions may cause short circuits between active regions of the semiconductor substrate beneath the bit lines and word lines.
It should also be noted that the topographic definition of the word lines, as obtained by photolithographic and either wet or dry etching operations performed on the conductive layer, can cause deformations in the floating gates as a result of the reiterative flushing involved to thoroughly remove the conductive layer from the regions not protected by a resist.
A first known proposal for planarizing semiconductor substrates with a plurality of floating gates is disclosed in European Patent Application 0 573 728 entitled "Processo EPROM a tovaglia" ("A Tablecloth EPROM Process") filed by S. Mazzali, M. Melanotte, L. Masini, M. Sali in 1989. The method disclosed in this document is illustrated in FIGS. 6A and 6B. Reference numerals in FIGS. 6A and 6B which are like, similar or identical to reference numerals in FIGS. 1 and 2 indicate like, similar or identical components. This method includes isolating the plurality of floating gates from one another by depositing a first dielectric layer 13 of the TEOS (TetraEthylOrthoSilicate) type. The thickness of the deposited TEOS layer 13 is quite substantial, being illustratively three times as great as the step between the substrate 1 and the upper end of the bit lines 6. A second dielectric layer 14 of the SOG (Spin-on Glass) type is then deposited over the first dielectric layer to planarize the surface of the semiconductor substrate. This deposition process includes a preliminary spinning step or step of spreading a highly viscous liquid material such as a SOG gel, followed by a solidification step using thermal polymerization treatments at a temperature in the 400.degree. C. range, for example. Thereafter, the planarized surface is subjected to selective etching in the respect of the polysilicon, in order to thoroughly remove the SOG dielectric layer 14 and confine the TEOS layer 13 to the voids 7 between the plural floating gates to form an electronic device 16 as illustrated in FIG. 6B.
However, this proposed approach has the serious drawback of requiring wet or dry etching steps to remove the excess insulating dielectric. These steps do etch away some of the originally substantial thickness of the TEOS dielectric, but also deteriorate the planarity previously achieved through the deposition of the SOG type of dielectric layer because of the different etching selectivity between TEOS and SOG. The deposition of dielectric layers of the TEOS type, especially thick ones, is always accompanied, in fact, by the formation of micro-voids or cracks from the deposition process itself (in particular the covering step) and stresses within the deposited material, whereby undesired contacts may be established between contiguous deposited layers.
The above observation is confirmed in an article "Planarized SiO.sub.2 Interlayer Formed by Two Step O.sub.3 /TEOS APCVD and Low Temperature Annealing" by Koji Kishimoto, Mieko Suzuki, Takeshi Hirayama, Yasuo Ikeda, and Youichirou Numasawa of NEC Corporation, Jun. 9-10, 1992, page 150, line 10, emphasizing the impossibility of using TEOS-type dielectric layers of substantial thickness, since they represent a source of mechanical failure which can only be avoided by adopting more elaborate growth methods.
Thus, what is needed is a method of depositing a layered dielectric structure, effective to promote planarization of a semiconductor substrate laid with a plurality of spaced bit lines, so as to accommodate the optional deposition of an overlying conductive layer while overcoming the aforementioned limitations and drawbacks besetting the prior art.